TSMC Unveils N3 Family Process Technology and 2nm Process Node Plans at North American Technology Symposium

Taiwan Semiconductor Manufacturing Company (TSMC) has updated its N3 family process technology progress and roadmap at the 2023 North American Technology Symposium. The company’s N3 process is its final high-performance node based on FinFET transistors and will live on for several years.

TSMC has already begun mass production on N3, also known as N3B, which uses extreme ultraviolet lithography (EUV) on up to 25 layers and can use EUV double patterning, which makes it expensive to use. However, TSMC expects the majority of its customers to opt for N3E, which uses up to 19 layers of EUV, does not rely on EUV double patterning, and has a wide process window and good yield. N3E is scheduled to enter mass production in the second half of 2023 and will be the basis for TSMC’s further 3nm evolution.

The big updates to TSMC’s N3 roadmap are for N3P and N3X. N3P is an optically scaled version of N3E that provides better performance, lower power consumption, and higher transistor density than N3E while maintaining compatibility with N3E’s design rules. N3X delivers extremely high performance at 3nm-class densities, offering high clock speeds for high-performance CPUs and processors.

TSMC plans to extend its N2 family with N2P, which features a backside power rail, promising better performance, lower power consumption, and higher transistor density. TSMC also plans N2X, a node designed for maximum performance and high voltage capability. TSMC’s standard N3 node features up to 25 EUV layers, some of which TSMC uses EUV double patterning to achieve higher logic and SRAM transistor density than N5.

TSMC will continue to optimize the transistor density of the N3 family with N3P, improving the characteristics of transistors based on N3E. The new node will also increase transistor density by 4% in a “mixed” chip design, which TSMC defines as a chip consisting of 50% logic, 30% SRAM, and 20% analogue circuitry. As part of the discussion on N3P, TSMC emphasized that the increased density was achieved by tuning the optical performance of the scanner.

TSMC’s N3X is a new addition to the N3 family and is aimed at high-leakage and power-tolerant applications. This node offers a 5% increase in performance for the same power or a 10% reduction in power for the same performance, compared to N3E. N3X features a high Vdd and Vt, enabling it to handle high-power applications such as AI accelerators and GPUs.

TSMC also announced updates on its 2nm process node plans. The company plans to use EUV on up to 50 layers for its 2nm process node, which is expected to enter risk production in 2024. The 2nm process node is expected to provide a 20-25% improvement in performance over N3. TSMC also plans to offer an optical shrink version of 2nm, called 2NP, which will provide a 10-15% increase in performance over 2N.

With N3E and N3P already in mass production and N3X and 2nm on the horizon, TSMC is well-positioned to meet the demand for high-performance, low-power chips.

Meet Vishak, TechLog360's Content Editor and tech enthusiast. With a Computer Science degree and a passion for all things tech, Vishak delivers the latest in hardware, apps, and games with expertise. Trusted for his in-depth reviews and industry insights, he's your guide to the digital world. Off-duty, he's exploring photography and virtual gaming landscapes.


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